1. Field of the Invention
The present invention relates to a driving method of a plasma display panel (PDP) and driving apparatus thereof, and a plasma display.
2. Discussion of the Related Art
Various flat panel displays such as the liquid crystal display (LCD), the field emission display (FED), and the PDP have been developed. Of these, the PDP has higher resolution, a higher rate of emission efficiency, and a wider view angle. Accordingly, the PDP is in the spotlight as a substitute display for the conventional cathode ray tube (CRT), especially in the large-sized displays of greater than forty inches.
A PDP shows characters or images using plasma generated by gas discharge, and it may include more than hundreds of thousands to millions of pixels arranged in a matrix. A PDP can be categorized as a direct current (DC) PDP or an alternating current (AC) PDP according to an applied driving voltage waveform and discharge cell structure of the PDP.
Electrodes of the DC PDP are exposed in a discharge space and the current flows in the discharge space when a voltage is applied, and therefore the DC PDP is problematic in that it requires a resistor for current limitation. On the other hand, electrodes of the AC PDP are covered with a dielectric layer, so the current is limited because of natural formation of capacitance components, and the electrodes are protected from ion impulses in the case of discharging. As such, the AC PDP usually has a longer lifespan than that of the DC PDP.
FIG. 1 shows a partial perspective view of an AC PDP.
As shown in FIG. 1, scan electrodes 4 and sustain electrodes 5 are formed in parallel pairs on a first glass substrate 1, and they are covered with a dielectric layer 2 and a protection film 3. A plurality of address electrodes 8 are formed on a second glass substrate 6, and the address electrodes 8 are covered with an insulator layer 7. Barrier ribs 9 are formed between and in parallel with the address electrodes 8 on the insulator layer 7, and phosphors 10 are formed on the surface of the insulator layer 7 and on both sides of the barrier ribs 9. The first and second glass substrates 1 and 6 are sealed together to form discharge spaces 11 therebetween so that the scan electrodes 4 and the sustain electrodes 5 are orthogonal to the address electrodes 8. A portion of the discharge space 11 at an intersection of an address electrode 8 and a pair of the scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.
FIG. 2 schematically shows a typical electrode arrangement of the AC PDP.
As shown in FIG. 2, the electrodes comprise an m×n matrix. The address electrodes A1 to Am are arranged in the column direction and the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn are alternately arranged in the row direction. The discharge cell 12 corresponds to the discharge cell 12 in FIG. 1.
FIG. 3 shows driving waveforms of the conventional PDP. The U.S. Patent Application Publication No. US 2003/0006945A1 by Lim et al. discloses a method for driving a conventional plasma display panel shown in FIG. 3. In the method, a scan low voltage Vscl is established to be lower than a voltage Vnf, which is applied last in the reset period.
As shown in FIG. 3, each subfield has a reset period, an address period, and a sustain period. In a rising period of the reset period, a voltage gradually rising to a voltage of Vset is applied to the scan electrodes Y1 to Yn, and therefore a weak discharge is generated in cells. In a falling period of the reset period, a voltage gradually falling to a negative voltage of Vnf is applied to the sustain electrodes while the sustain electrodes X1 to Xn are biased at a predetermined voltage Ve, and therefore wall charges are substantially eliminated. Accordingly, a wall charge state of each cell is reset. In the address period, a pulse voltage Vscl, which is lower than the voltage of Vnf, is sequentially applied to the respective scan electrode lines while the scan electrodes Y1 to Yn are biased at a predetermined voltage Vsch. At this time, an address voltage Va is applied to the address electrodes A1 to An in order to select a discharge. As shown, in the address period, the address voltage Va is reduced by establishing the scan low voltage Vscl sequentially applied to the scan electrodes to be lower than the voltage of Vnf, which is applied last in the reset period. In the sustain period, a discharge for substantially displaying an image in the addressed cell is generated by alternately applying a sustain-discharge voltage Vs to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn.
In the conventional driving method as shown in FIG. 3, the wall charges are reduced in the scan electrode lines (e.g., Y0 to Yn lines) which take a relatively long time to be addressed in the wall charge state generated in the reset period, and therefore an address operation may not be properly performed.
FIG. 4 shows driving waveforms of a conventional PDP. U.S. Pat. No. 6,294,875 by Kurata et al. discloses a method for driving the conventional PDP shown in FIG. 4. In this method, a field is divided into eight subfields, and a waveform applied in the reset period of a first subfield is established to be different from waveforms applied in the reset periods of second through eighth subfields.
As shown in FIG. 4, each subfield has a reset period, an address period, and a sustain period. A waveform in the reset period of the first subfield is different from a waveform in the reset period of the second subfield. A gradually rising and falling ramp waveform is applied to the scan electrodes Y1 to Yn in the reset period of the first subfield, and therefore the discharge cells are reset. In the address period, a scan low voltage (GND) is sequentially applied to the scan electrodes, and an address voltage Va is applied to the address electrodes in order to select cells. In the sustain period, a sustain-discharge pulse voltage Vs is alternately applied to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn.
A voltage level of a last sustain pulse applied to the scan electrodes Y1 to Yn in the sustain period of the first subfield is substantially the same as that of a voltage of Vr of the reset period, and a voltage of (Vr-Vs) corresponding to a difference between the voltage of Vr and a sustain voltage Vs is applied to the sustain electrodes X1 to Xn. A discharge is generated from the scan electrodes Y1 to Yn to the address electrodes A1 to Am, and the sustain discharge is generated from the scan electrodes Y1 to Yn to the sustain electrodes X1 to Xn in the discharge cell selected in the address period by the wall voltage formed by the address discharge. The discharge corresponds to the discharge generated by a rising ramp voltage in the reset period of the first subfield. No discharge is generated in the discharge cell which is not selected because no address discharge has been generated.
In the reset period of the second subfield, a voltage of Vh is applied to the sustain electrodes X1 to Xn, and a ramp voltage gradually falling from the voltage of Vq to 0V is applied to the scan electrodes Y1 to Yn. That is, a voltage corresponding to the falling ramp voltage applied in the reset period of the first subfield is applied to the scan electrodes Y1 to Yn. A weak discharge is generated in the selected discharge cell and no discharge is generated in the discharge cell which is not selected in the first subfield.
In reset periods of the other subfields, a waveform corresponding to the waveform in the reset period of the second subfield is applied. In an eighth subfield, an erasing period is formed after a sustain period. In the erasing period, a ramp voltage gradually rising from 0V to a voltage of Ve is applied to the sustain electrodes X1 to Xn. The wall charges formed in the discharge cell are eliminated by the ramp voltage.
In the conventional waveform as shown in FIG. 4, an address operation in a subfield having a period for applying a rising and falling ramp voltage as in the first subfield is not performed in the same condition as an address operation in a subfield having a period for applying a falling ramp voltage as in the second subfield. That is, all cells are discharged and reset in the reset waveform of the first subfield. However, in the reset waveform of the second subfield, cells discharged in a previous subfield are reset. Therefore, an address misfiring discharge may be generated because the wall charges and priming particles are reduced when the cells which were not discharged in the previous subfield are addressed in a subfield as in the second subfield.